"Flash" erasable programmable read only memories (EPROMs) derive their name from the manner in which they are erased. Flash EPROMs are typically designed with a number of cells having a common source, allowing the cells to be erased simultaneously by Fowler-Norheim tunneling, via their sources. Erase is typically accomplished by applying a positive voltage to the source relative to the control gate.
During operation of flash EPROMs, selected cells are read by applying a "select" voltage to the control gate of the cells. In most flash memory organizations, each row of cells includes a common control gate. At the same time a row to be read is selected, rows that are not read have a "de-select" voltage applied to the control gate of their respective cells. Proper operation of the flash cells requires that programmed cells remain off when selected, and erased (non-programmed) cells be turned on when selected. The current provided by a selected, erased cell is often referred to as the "read current." In addition, all cells, whether programmed or not, must remain turned off when de-selected. A vexing problem associated with flash EPROMs is that of "over-erase." Over-erase occurs when a cell's threshold voltage is lowered during an erase operation to the point where it cannot be sufficiently turned off when de-selected.
The causes of, and some solutions to, the over-erase problem are set forth in commonly-owned U.S. Pat. No. 5,416,738 issued on May 16, 1995 to Ritu Shrivastava. Included within Shrivastava is a flash EPROM method utilizing a negative read de-select voltage. The negative read de-select voltage "captures" a range of over-erased cells, by allowing some over-erased cells to be turned off when de-selected.
Attention is further directed to the review of flash EPROMs and "conventional" EEPROMs also set forth in Shrivastava.
A converging erase scheme is described in "A Self-Convergence Erasing Scheme for a Simple Stacked Gate Flash EEPROM," in IEDM, pp. 307-310, (1991) by Yamada et al. Yamada et al. discusses the property of erase convergence. Erase convergence occurs when a positive voltage is applied to the source of a flash EPROM cell, and the control gate and drain of the cell are grounded. Yamada et al. shows that the threshold voltage will converge on a "steady-state" threshold voltage (referred to as Vtss herein). The convergence phenomena occurs in those cases where the threshold voltage (Vt) of the cell is less than the cell's ultra-violet erased threshold voltage (Vt-uv), and includes cells having a Vt greater than or less than Vtss. As Vtss is dependent upon Vt-uv, Yamada et al. suggests using channel doping to control Vtss.
U.S. Pat. No. 5,233,562 issued to Ong et al. on Aug. 3, 1991, describes a flash EPROM cell repair scheme using the convergence property to repair over-erased cells. In a drain disturb repair, the control gate and source of a cell are grounded, while a positive voltage is applied to the drain. Similarly, in a source disturb repair, the control gate and drain are grounded, while a positive voltage is applied to the source. In a gate disturb repair, the drain and source are grounded, and a positive voltage is applied to the gate.
Referring now to FIGS. 1a-1c, the drawbacks inherent in the above referenced prior art over-erase repair schemes are illustrated. FIG. 1a illustrates the ideal case where the desired erased cell threshold voltage (Vtd) is equal to the steady-state convergence threshold voltage, Vtss. In this case, prior art methods are effective in eliminating the over-erase problem. As shown in FIG. 1a, the over-erased cell threshold voltage (Vtc) begins in an over-erased condition (Vtc&lt;Vtd). When the source and control gate are grounded, and a positive voltage applied to the drain, the Vtc converges to Vtss. Because in this ideal case Vtss=Vtd, the cell's final erased threshold voltage is Vtd, and the cell operates within desired parameters.
FIG. 1b illustrates a non-ideal case where prior art converging over-erase repair methods are not effective. As set forth in the figure, for this case, Vtss is less than Vtd. Variations between Vtss and Vtd can result from fabrication process variation. As a result, after over-erase repair, the cell's Vtc remains below Vtd, and the "repaired" cell essentially remains over-erased. Shrivastava, referred to above, teaches a read biasing condition wherein the de-select voltage is negative, thus maintaining over-erased cells in a non-conducting state. Further, commonly owned U.S. Pat. No. 5,513,147, entitled ROW DRIVING CIRCUIT FOR FLASH MEMORIES, issued to Bruce L. Prickett. Jr. on Apr. 30, 1996 and incorporated by reference herein, teaches a wordline driving circuit for providing a negative read de-select voltage.
FIG. 1c illustrates a second non-ideal case where Vtss is greater than Vtd. In this case, after repair, the over-erased cell has a Vtc that is above Vtd. It is "soft-programmed." To counter-act such a result, an iterative and/or slower repair approach is required. This adds to the amount of time required to properly erase the cells.
FIG. 1d illustrates the distribution of erased threshold voltages (Vte) in a flash device. Also set forth in the diagram are representations of the control gate read select voltage (Vcg select) and de-select voltage (Vcg de-select). Those cells falling well between Vcg select and Vcg de-select will provide proper device operation. Those cells falling below Vcg de-select (commonly called "tail" cells) will not be sufficiently turned off when de-selected.
U.S. Pat. No. 5,424,991 issued to Genda Hu on Jun. 13, 1995 discloses a floating gate memory with a uniformly erased threshold voltage. According to the '991 patent, the cells of an array are first programmed and then erased to a threshold voltage below a desired threshold voltage. The threshold voltages of the cells are then "equalized" to the desired threshold voltage by the application of an equalization voltage to the control gates of the cells. A drawback to the Hu invention is that unless the cells are initially erased to a voltage that is close to the desired threshold voltage, large amounts of current are drawn during the equalization steps. Further, simultaneous equalization of multiple bit lines can result in non-uniform threshold voltages due to variations in the source resistance of bit lines, this is particularly true if large amounts of current are drawn during equalization.
Clearly it would be desirable to provide an over-erase method that addresses the problems set forth above.